1. Technical Field
The present invention relates generally to the field of semi-conductor manufacturing and, more specifically, to a method for forming interconnections in memory cells.
2. Background Art
The need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced.
The push for ever increasing device densities is particularly strong in Dynamic Random Access Memory (DRAM) markets. Each DRAM cell consists of a transfer device, typically a MOS transistor, and a storage capacitor. Two types of storage capacitors are commonly used today, stack capacitors and trench capacitors. Trench capacitors increase capacitance by extending into the storage node deeply into the substrate. One particular area of concern in trench capacitor DRAM technology is the connection between the trench storage capacitor and the transfer device.
Several different methods and structures have been used to provide connection between the transfer device and the trench storage capacitor. These structures have been generically referred to as xe2x80x9cstrapsxe2x80x9d.
One method for forming straps involves selectively growing silicon between the capacitor and the transfer device after the spacers on the gate conductor have been formed and the junctions implanted. Following this, salicide is formed, consuming the selective silicon to form a low resistence strap. This process has the advantage of not requiring extra mask steps for the strap, but it has the disadvantage of increasing word pitch because the passing word line cannot pass over the strap contact.
Another method for forming straps involves photolithographic definition of an area to form the strap. In this method, after source-drain implantation, a thin layer of silicon nitride is deposited on the chip. A contact hole is defined photolithographically in the strap area as the trench top oxide is etched in each cell, exposing the doped trench polysilicon and the source-drain diffusion that are to be connected. A blanket layer of intrinsic polysilicon is then deposited, and the wafer is annealed to diffuse dopant up into the intrinsic polysilicon from the trench and diffusion tops. The result is a doped polysilicon layer bridging the trench and the source-drain diffusion. The remaining intrinsic polysilicon is then removed by a selective wet etch, isolating the cells from one another. One disadvantage of this process is that the selectivity of the wet etch must be carefully controlled. In particular, the wet etch must remove undoped polysilicon to avoid strap to strap shorts, while the doped polysilicon must remain. Another disadvantage is that the strap is not self aligned to the trench and thus tight photolithographic alignment control is required to assure connection between the trench and the source-drain diffusion.
Another method for connecting the storage capacitor to the transfer devices uses a xe2x80x9cburied strapxe2x80x9d. Buried straps are formed using outdiffusion from the sidewall of the storage capacitor in the silicon substrate. In particular, the portion of the oxide collar in the trench capacitor where the buried strap is to be formed is removed. Polysilicon is then blanket deposited in the place of the removed oxide collar. The wafer is then annealed, causing the dopant to outdiffuse from inside the trench capacitor and into the buried strap region. Thus, outdiffusion of the dopant from the storage capacitor polysilicon merges with the source-drain diffusion to complete the contact between the transfer device and the storage capacitor. To minimize the buried strap diffusion from affecting device characteristics, arsenic, which diffuses slowly is preferred as the n+type dopant in the trench polysilicon for the n-channel transfer device.
Turning now to FIG. 22, a prior art merged isolation and node trench (MINT) DRAM cell using a buried strap is illustrated schematically. The cell includes a substrate 10 with a p-type well 12 formed at its top portion. At the upper surface of the p-type well 12 a transfer device 14 is formed that includes a control gate 16 that is responsive to a word access line of the DRAM array support circuits, not shown. Also at the upper surface is a passing word line 17, used to access adjacent devices not shown. The transfer device 14 couples data between bit line diffused n+ region 18 and diffused n+ region 20 through the channel region formed in p-type well 12. A shallow trench isolation region 30 serves to isolate this device from adjacent devices not shown. A deep trench 22 is formed into the substrate 10, with deep trench 22 adjacent to n+ region 20. A buried n+ plate 25 is diffused from the deep trench walls from a deposited and recessed arsenic doped glass. Inside deep trench 22 is formed the capacitor storage node comprising n+ type polysilicon electrode 24. The buried plate 25 is separated from the polysilicon electrode 24 by a thin dielectric layer. At the top of the storage trench 22 is a thick isolating collar 28 which serves to prevent parasitic vertical device leakage. A portion of the thick isolating collar 28 is removed to allow n+ region 20 and the polysilicon storage node 24 to be connected by a buried strap 11. Again, this buried strap 11 is formed by removing a portion of the isolating collar 28 between the polysilicon electrode 24 and the n+ region 20. The cell is then annealed, causing n+ dopant to diffuse from the polysilicon electrode 24 and into the adjacent substrate, forming buried strap 11.
One problem with buried straps is that the method which forms the buried strap results in a buried strap which is deeper than the optimum depth of the n+ diffusion of the transfer device. The deeper buried strap degrades the sub threshold leakage of the adjacent transfer device. This results in unwanted loss of stored charge and shortening of the retention time. Therefore, to avoid the sub-threshold leakage problem, either the gate length must be designed longer than the minimum dimension, or the distance between the gate and the strap must be designed large enough to keep the buried strap away from the device. Either of these solutions makes it almost impossible to effectively reduce the size of the DRAM cell.
Thus, without an improved method and structure for connecting between storage capacitors and transfer devices, the density of memory devices will be limited.
Accordingly, the present invention provides unique structure for connecting between a storage capacitor and a transfer device in a memory cell and a method for fabricating the same. The preferred embodiment of the present invention forms a capacitor structure having a xe2x80x9clipxe2x80x9d at its top on the side the connection is to be made. To form the connection, dopant is diffused from the lower surface of the capacitor step and into the substrate, forming a surface strap to connect between the storage capacitor and the transfer device. This surface strap has the advantage of being self aligned with the storage capacitor and the transfer device, facilitating higher memory cell densities. The present invention can be used to form connections between storage capacitors and memory cells in a wide variety of devices.